Part 1: The Era of Substrates — The Empire of Sand, Back onto Glass
- Source: https://x.com/nuttycld/status/2022282936603787765?s=46
- Mirror: https://x.com/nuttycld/status/2022282936603787765?s=46
- Published: 2026-02-13T12:13:18+00:00
- Saved: 2026-02-14
Content
For the past half-century, humanity has been obsessed with making things "smaller." That was the only way to pack more transistors onto a single chip. Shrinking transistors to 10nm, 5nm, and 3nm was the very definition of semiconductor technology. But eventually, the laws of physics issued a cold verdict: "You cannot go any smaller."
In response, people changed their thinking.
"If we can't make the individual unit smaller, why not combine several of them to build something larger?"
This single question changed the rules of the game. Now, the core focus is no longer the microscopic circuits inside the chip, but the "bridges" connecting chip to chip, and the "ground" that supports them. The war of the nanometer (nm) has ended; the war of the micrometer (μm) has begun.
And sitting right in the center of that battlefield is transparent glass.
- Why Chips Can't Get Any Bigger
AI models are getting larger, and the number of transistors that need to be integrated on a chip keeps increasing. To fit more transistors, the chip must grow in size — but there is a ceiling that cannot be surpassed
Circuit patterns on a chip are etched using light, and there's a limit to how large an area that light can expose in a single shot. This is the reticle limit — roughly 858 mm² with current technology. NVIDIA's GH100 die is already 814 mm², practically bumping against the ceiling.
But size aside, there's another problem. Imagine drawing a grid on a large canvas. Each square is one chip. Now dip a small brush in paint and flick it once across the canvas. Every square hit by a droplet is defective. If the squares are small, plenty survive unscathed. But make them larger? A single droplet touching a square ruins the whole thing. The bigger the square, the faster the survival rate plummets.
This is the yield problem. Can't go smaller. Can't go bigger. A single monolithic chip is a dead end.
So the industry's answer was to go in reverse.
- Break Apart, Then Reconnect
Imagine 3D-printing Hogwarts Castle in one piece. If a single spot goes wrong mid-print, you throw the whole thing away. But if you build it out of Lego? One bad brick — just swap it out.
Chiplets are that Lego. You break one massive chip into smaller pieces, manufacture them separately, then stitch them back together. Smaller chips have higher yields, so costs drop. They don't bump into the reticle limit. Better yet, each chiplet can use a different process node — the compute cores on cutting-edge 3nm, the I/O circuits on cheaper 6nm. Marble for the living room, brick for the warehouse. A rational choice.
NVIDIA's Blackwell bonds two near-limit-sized dies into a single GPU. Intel's Ponte Vecchio assembles 47 chiplets into one processor.
But there's a critical price to pay.
Inside a single chip, everything was connected by internal wiring — fast, wide, energy-efficient. The moment you split a chip apart, conversations that used to happen internally now have to travel outside the chip. It's like a team that used to meet face-to-face in one building suddenly scattered across separate offices, forced onto video calls.
The quality of those video calls determines the entire team's productivity. If the links between chiplets aren't as fast as the internal wires they replaced, there's no point in splitting them up in the first place.
Making great chips is no longer enough. The era belongs to those who can connect them.
- A Bacon Egg McMuffin (CoWoS)
The structure that stitches chiplets together looks like a Bacon Egg McMuffin — minus the top bun.
The English muffin at the bottom is the substrate. The ground that supports everything. It delivers power to the chips, connects them to the outside world, and physically holds the entire package together.
The bacon on top is the chip — GPU, HBM memory, the components that actually compute.
When there was only one chip, you just placed the bacon on the muffin and called it a day. But in the chiplet era, the bacon slices need to talk to each other. So a layer of egg was inserted between the muffin and the bacon: the interposer — a bridge that connects chip to chip at ultra-high speed.
You've probably heard the acronym CoWoS. Chip-on-Wafer-on-Substrate. C is the chip (bacon), W is the interposer (egg), S is the substrate (muffin). The name is the structure.
The critical question in this architecture comes down to one thing: what do you make the egg and the muffin out of? That decision determines performance, cost, and how many AI chips the world can actually produce.
- Organic's 25-Year Reign
To understand the story properly, you need to know the reigning king.
The vast majority of substrates today are organic — layers of resin and fiberglass stacked together. Stable and cheap. Since displacing ceramic substrates in the late 1990s, organic substrates have been the quiet foundation of the semiconductor industry for a quarter century.
Twenty-five years is long enough for almost everything to change. In that time, transistors shrank from hundreds of nanometers to 3nm. Chip computing power jumped by tens of thousands of times. But the substrate? It kept quietly doing its job on the same basic material.
AI shattered that quiet.
To see the problem, you need to understand the two tests a good substrate must pass.
Test one: survive the heat. All materials expand when heated. When an AI accelerator burns hundreds of watts and heats up, the chip (silicon) and the substrate beneath it both expand — but at different rates. It's like two people with different stride lengths trying to run a three-legged race. This difference in expansion rate is the coefficient of thermal expansion (CTE). Organic substrates expand six to seven times more than silicon. For small packages, you could ignore this. But when packages grow to AI-chip scale, the warpage becomes catastrophic. In the worst case, solder joints crack apart.
Test two: protect the signal. When electrical signals pass through a substrate, the substrate material absorbs signal energy. Think of a car on a dirt road. At low speeds, it's fine. But at the ultra-high frequencies AI chips demand, the signal gets smeared beyond recognition. Restoring a smeared signal forces the DSP to work overtime, which consumes power, generates heat, and the heat further degrades the signal — a vicious cycle. The same physical barrier we encountered discussing copper's limits in The Age of Light plays out identically inside the substrate.
Organic substrates passed both tests comfortably for 25 years. Packages were small. Speeds were slow. But in front of AI chips, both tests collapsed simultaneously.
The throne began to shake.
- Silicon's Coup
The first place organic substrates surrendered was the middle layer directly linking chip to chip — the interposer. For this bridge, which must transmit massive volumes of signals at high speed, organic materials simply couldn't cope.
In 2012, TSMC's answer was straightforward:
"Let's use silicon — the same material we make chips from — to build the bridge."
This is the heart of CoWoS. Lay a silicon slab between chips as the interposer. Same silicon, so the thermal expansion mismatch shrinks. Manufactured with semiconductor processes, so wiring finer than a fraction of a hair's width becomes possible. Without silicon interposers, today's AI chips would not exist.
The problem is that silicon interposers are made on semiconductor wafers. They don't require the most cutting-edge process nodes, but they still occupy TSMC's cleanrooms, wafer capacity, and packaging lines.
Back to the McMuffin. In a kitchen with only four burners, frying the egg (interposer) takes two. That leaves too few burners to cook all the bacon (chips) you need. Building bridges competes for the same resources as building chips. That is the essence of the bottleneck.
Cost is steep, too. A single large silicon interposer runs well over $100, and the interposer alone can account for more than half the total packaging cost. By 2028, packaging a single top-tier AI chip is projected to cost around $1,300.
Size hits a wall as well. Silicon interposers are cut from round wafers, so the same yield logic applies. Bigger interposers mean fewer per wafer and higher defect rates.
Silicon accomplished what organic substrates could not. But the price was too high. At a time when AI chip demand is exploding, the best bridge has become the biggest bottleneck.
- Glass Throws Down the Gauntlet
Organic substrates are cheap but hit a wall in front of AI chips. Silicon interposers deliver top performance but devour packaging resources and resist scaling. Between the two, there's an empty seat.
That's where glass steps in.
"Glass substrate" is an umbrella term, but in reality two completely different paths coexist.
Path one: replace the interposer with glass. Take the bridge that silicon occupied and build it instead with the large-area glass processing equipment of the display industry. In McMuffin terms, you're swapping in an ingredient for the egg that doesn't need a burner. Burners freed up mean more bacon (chips) you can cook. This is the path Samsung is targeting by 2028.
Path two: replace the substrate itself with glass. A fundamentally different logic — break through the performance ceiling of organic substrates at the base level. More expensive than organic, but worth it. This is the path Intel has invested over $1 billion in.
Same "glass," but the problems they're solving are different.
- Material Properties That Shake the Throne
Glass can throw down the gauntlet because it delivers overwhelming results in the exact two tests where organic substrates failed.
Thermal expansion. Organic substrates: 17–20 ppm/°C. Silicon: roughly 3 ppm/°C. A six-to-seven-fold gap. Glass can be tuned in composition to approach 3 ppm/°C — meaning it can match silicon's stride. This is the most fundamental advantage. Package sizes that are impossible on organic substrates become feasible on glass.
Signal loss. If organic substrates are a dirt road, glass is freshly paved asphalt. Signal loss through glass can be more than 10× lower than through organic substrates. Less signal smearing means less burden on recovery circuits, less power consumption, less heat, and the vicious cycle breaks.
Those two alone are significant enough, but glass has two more properties that organic substrates can never imitate.
Its surface is extraordinarily smooth. If an organic substrate's surface is a dirt road, a glass surface is a skating rink. Hybrid bonding — an emerging technology that presses copper pads directly together without solder — requires exactly this kind of smoothness as a precondition. It can shrink the pitch between connection points from tens of micrometers to below 10 micrometers, creating tens of times more connections in the same area. Impossible on organic substrates. Possible on glass.
And glass is transparent. Light passes through it, which means optical waveguides can be embedded directly inside the substrate. The stage for optical interconnects discussed in The Age of Light expands from on top of the chip to inside the substrate itself. A world where electrical signals convert to optical signals and travel between chips — glass is the material that can become the foundation of that world.
- Glass Breaks
Of course, if glass were a silver bullet, it would already be on the throne.
Start with the most fundamental issue: glass breaks. During cutting, drilling, and handling, microscopic cracks form. As a chip powers on and off tens of thousands of times — expanding and contracting with each cycle — those cracks can propagate catastrophically. The industry is suppressing this with edge-finishing techniques and strengthening treatments, but long-term reliability data across thousands of thermal cycles is still insufficient.
Thermal conductivity is two orders of magnitude lower than silicon. Silicon conducts heat at roughly 130–150 W/m·K. Glass: about 1 W/m·K. But this weakness comes with an interesting twist. Remember glass's transparency — if waveguides are embedded in the substrate and data travels as light, the signals passing through the substrate generate almost no heat. Low thermal conductivity stops being a fatal flaw. Glass's weakness and optical interconnects' strength complement each other.
There's another paradox. The very property that keeps glass from absorbing signals becomes an unexpected weakness in power delivery. In a noisy café, chatter from the next table disappears into the background. But in an empty concert hall, a single cough echoes everywhere. A glass substrate is that empty concert hall. Tiny noise from power delivery circuits doesn't get absorbed — it reverberates, causing the power supply to ripple instead of flowing cleanly.
Reliability, thermal dissipation, power noise — three mountains stand before glass. The possibilities have been proven in the lab, but these mountains must be crossed before glass can step onto a mass-production line.
Epilogue: The Stage Is Shifting
The blade that once split transistors has dulled. In its place, the needle and thread that stitch chips together are growing sharper. The substrate is no longer a simple plastic pedestal. It is itself a massive circuit — a second semiconductor that sets the performance ceiling of the entire system.
By 2028, glass will begin to take its place at the heart of cutting-edge AI accelerators. And beyond that — a substrate where light flows through glass, where electrical signals become optical signals traveling between chips — that world is waiting.
The possibilities have been confirmed. But between the lab's glass and the factory's production line, many mountains remain. To cross them, trillions of won in capital are moving at this very moment.
Who crosses the threshold of mass production first. Whose capital becomes the capital that matters. The map of that enormous money game will be unfolded in Part 2.
Part 1 — Key References
Chip Size Limits & Chiplet Architecture
NVIDIA, "H100 Tensor Core GPU Architecture" (March 2022)
NVIDIA, GTC 2024 Keynote, Blackwell Architecture (March 2024)
Intel, "Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing" (ISSCC 2022)
Packaging Technology
TSMC, "CoWoS® Platform" (tsmc.com/3dfabric)
SemiAnalysis, "AI Expansion — Supply Chain Analysis for CoWoS and HBM" (July 2023)
Bloomberg Intelligence, "Advanced Semiconductor Packaging Market Could Reach $80 Billion by 2033" (October 2025)
Glass Substrate Technology & Material Properties
Intel, Press Release, "Unveils Industry-Leading Glass Substrates to Meet Demand for More Powerful Compute" (September 2023)
Semiconductor Engineering, "Glass Substrates Gain Momentum"
MDPI, "A Review of Glass Substrate Technologies"
Key Industry Developments
NIST / U.S. Department of Commerce, "Preliminary Terms with Absolics" (2024)
Samsung Electro-Mechanics, "Signs MOU with Sumitomo Chemical Group for Glass Core JV"
TrendForce, "Intel Reportedly Starts Glass Substrate Licensing" (2025)
Market Outlook
Bloomberg Intelligence, "Advanced Semiconductor Packaging Market" (October 2025)
Future Markets Inc., "The Global Market for Glass Substrates for Semiconductors 2026–2036"
Link: http://x.com/i/article/2021901179622764548